In the field of semiconductor devices, in which scaling is proceeding, various investigations have been made on materials having a low dielectric constant (hereinafter also referred to as “low-k materials”) and having a porous structure, as interlayer insulating layers for semiconductors.
In such porous interlayer insulating layers, increasing the porosity thereof with a view to further lowering the dielectric constant results in facilitation of entry of a metal component that is to be embedded as a wiring material such as copper, a plasma component (at least one of a radical or an ion; the same shall apply hereinafter) generated through a plasma treatment, or the like into minute openings of the semiconductor interlayer insulating layers, and thus results in an increase in the dielectric constant or occurrence of a current leakage in some cases.
Penetration of the metal component, the plasma component, or the like also occurs in non-porous interlayer insulating layers in some cases, which results in an increase in the dielectric constant or occurrence of a current leakage in some cases, similar to the case of porous interlayer insulating layers.
In order to deal with the above issue, a technique has been studied in which an interlayer insulating layer (in a case in which the interlayer insulating layer is a porous interlayer insulating layer, minute openings (pores) that are present in the porous interlayer insulating layer) is covered (sealed) using a polymer having a cationic functional group.
For example, a sealing composition for a semiconductor that contains a polymer having two or more cationic functional groups and a weight average molecular weight of from 2,000 to 100,000 is known as a sealing composition for a semiconductor that has an excellent pore-covering property (sealing property) with respect to porous interlayer insulating layers (see, for example, International Publication WO 2010/137711 pamphlet).
Furthermore, a semiconductor substrate is known which has a configuration having: an interlayer insulating layer having a recess portion (a trench or a via); and a wiring, at least a part of the surface of the wiring being exposed on at least a part of the bottom face of the trench or via. In the semiconductor substrate having the configuration described above, another wiring or the like is embedded in the trench or via in a subsequent step, whereby the wiring embedded in the trench or via and the wiring of which a part was exposed on the bottom face of the trench or via are electrically connected to each other (see, for example, International Publication WO 2009/153834 pamphlet).